In the semiconductor industry, microlithography (or simply lithography) is the process of printing the circuit patterns on a semiconductor wafer (for example, a silicon or gallium arsenide wafer). Currently, optical lithography is the predominant technology used in volume semiconductor manufacturing. Optical lithography employs light in the visible to deep ultraviolet spectrum range to expose the resist on a wafer. In the future, extreme ultraviolet (EUV) and soft x-rays may be employed. Following exposure, the resist is developed to yield a relief image.
In optical lithography, a photomask (often called a mask or a reticle) is first written using electron-beam or laser-beam direct-write tools. A typical mask for optical lithography consists of a glass (or quartz) plate of six to eight inches on a side, with one surface coated with a thin metal layer (for example, chrome) of a thickness of about 100 nm. The chip pattern is etched into the metal layer, hence allowing light to transmit through. The area where the metal layer is not etched away blocks light transmission. In this way, a pattern may be projected onto a semiconductor wafer.
The mask contains certain patterns and features that are used to create desired circuit patterns on a wafer. The tool used in projecting the mask image onto a wafer is called a stepper or scanner (hereinafter collectively called “exposure tool”). FIG. 1 is a block diagram of an optical projection lithographic system 10 of a conventional stepper including an illumination source 12, an illumination pupil filter 14, a lens subsystem 16a-c, a mask 18, a projection pupil filter 20, and a wafer 22 on which the aerial image of mask 18 is projected.
Illumination source 12 may be laser source operated, for example, at UV (ultra-violet) or DUV (deep ultra-violet) wavelengths. The light beam is expanded and scrambled before it is incident on illumination pupil 14. Illumination pupil 14 may be a simple round aperture, or have specifically designed shapes for off-axis illumination. Off-axis illumination may include, for example, annular illumination (i.e., the pupil is a ring with a designed inner and outer radius), quadruple illumination (i.e., the pupil has four openings in the four quadrant of the pupil plane), and other shapes like dipole illumination.
After illumination pupil 14, the light passes through the illumination optics (for example, lens subsystem 16a) and is incident on mask 18. Mask 18 contains the circuit pattern to be imaged on wafer 22 by the projection optics. As the desired pattern size on wafer 22 becomes smaller and smaller, and those patterns becomes closer and closer to each other, the lithography process becomes more challenging. In an effort to improve imaging quality, current processing techniques employ resolution enhancement technologies (“RET”), such as, for example, optical proximity correction (“OPC”), phase shift masks (“PSM”), off-axis illumination (“OAI”), condenser and exit pupil filters, and so on.
Many of the RET technologies are applied on or directly to mask 18. For example, OPC and PSM, which modify the light wave to (1) compensate for the imperfection of the imaging property of the projection optics, for example, the OPC technology is used to compensate the optical proximity effect due to light interference, and/or (2) take advantage of designed light interferences to enhance the imaging quality, for example, the phase shift mask technology is used to create phase shifting between neighboring patterns to enhance resolution.
Notably, mask 18 may not be “perfect” due to its own manufacturing process. For example, corners on mask 18 may not be sharp but may be rounded and/or the linewidth may have a bias from design value where the bias may also depend on the designed linewidth value and neighboring patterns. These imperfections on mask 18 may affect the final imaging quality.
The projection optics (for example, lens subsystems 16b and 16c, and projection pupil filter 20) images mask 18 onto wafer 22. In this regard, the projection optics includes a projection pupil filter 20. Projection pupil filter 20 limits the maximum spatial frequency of the mask pattern that can be passed through the projection optics. A number called “numerical aperture” or NA often characterizes projection pupil filter 20. There are also proposed RET techniques that modify projection pupil filter 20, which is generally called pupil filtering. Pupil filtering may include modulation for both the amplitude and the phase on the passing light beams.
Due to the wavelength of light being finite, and current techniques employing wavelengths that are larger than the minimum linewidth that is printed on wafer 22, there are typically significant light interference and diffractions during the imaging process. The imaging process is not a perfect replication of the pattern on mask 18. Current techniques employ physical theory to model this imaging process. Further, due to the high NA value of current exposure tools, different polarizations of the light provide different imaging properties. To more accurately model the lithography process, a vector-based model may be used.
The projection optics may be diffraction-limited. However, lens subsystem 16b and 16c in the projection optics are most often not completely “perfect.” These imperfections may be modeled as aberrations, which are often abstracted as some undesired phase modulation at the plane of projection pupil filter 20, and are often represented by a set of Zernike coefficients. After the light finally reaches the surface of wafer 22, they will further interact with the coatings on wafer 22 (for example, the photo-resist). In this regard, different resist thickness, different optical properties of the resist (for example, its refractive index), and different material stack under the resist (for example, bottom-anti-reflection-coating or BARC), may further affect the imaging characteristics. Some of these effects may also be abstracted by a modulation at the pupil plane.
When the resist is exposed by the aerial image and thereafter baked and developed, the resist tends to undergo complex chemical and physical changes. First principle and empirical models have been developed to simulate these processes.
When wafers are printed using an exposure tool, ideally, wafer 22 should be placed exactly at the focal plane of the projection optics, or a designated location away from the focal plane. However, due to the imperfect mechanical control of exposure tools, there is always a small deviation between the designated plane and the actual wafer plane. That deviation is called defocus, or sometimes just called “focus,” and represented by a distance unit, e.g., 50 nm. The defocus introduces additional imperfections in the imaging path, and can also be characterized by a phase modulation at the pupil plane.
Furthermore, all wafers, and dice on the wafers, are ideally exposed by a designated amount of exposure dose, e.g., 20 mJ/cm2. However, due to the imperfections in the illumination control and changes in the reflectivity and uniformity of the film stacks on the wafers being patterned, there is always a small deviation between the ideal exposure dose and the actual exposure dose deposited on a die. That deviation is called exposure dose variation, or sometimes just called “exposure,” and is represented by a percentage deviation from the ideal exposure dose, e.g., 10%.
The combination of focus and exposure errors means that the dimensions of the wafer features that are patterned may not match exactly with the dimensions required by the design. Since every structure responds differently to focus and exposure errors in different ways depending on the width, shape, and local environment of the specific structure, it is not possible to describe the response of every individual structure in a circuit pattern with a limited set of figures of merit.
In practice, the most common metric used to characterize a lithography process is the width of the smallest features being patterned on a given process layer for a given technology. This minimum dimension is referred to as the “critical dimension” or CD. While critical dimensions are actually intended to represent the three dimensional resist profile, the term CD is usually associated with a one-dimensional slice through the resist line, also referred to as the linewidth. In a looser definition, the term CD is often used to refer to any linewidth measurement even if it is not the minimum dimension on the device.
Under a certain lithographic setting (e.g., exposure tool, wavelength, NA, and so on), the amount of defocus and exposure dose variations that a circuit design can tolerate, while still producing functional chips, is called the design's “process window.” The process window is often characterized as an area or region in the two-dimensional F-E plot, where “F” is defocus, and “E” is exposure dose variation. Such a plot may also be referred to as an “ED tree”, so-called because of the tree-shaped process window which results when exposure (E) is plotted on the x-axis and defocus (D) is plotted on the y-axis. Some RET techniques (e.g., PSM, scattering bars in OPC, OAI) can enhance the process window for a certain circuit design. The settings of the exposure tool (e.g., NA) also have a big impact on the process window.
FIG. 2 shows one example of a process window 30 in the F-E plane. When a wafer is exposed in a F-E condition within process window 30, the chips made from dice on that wafer will be functional. When the wafer is exposed in a F-E condition outside process window 30, the chips from the wafer will not be functional. The larger process window 30, the more robust the circuit design is, and will have higher yield in manufacturing.
A process window for a lithography process is further limited because different patterns within a circuit design have different process windows. These differences may include shifts in the best focal plane position, shifts in the best exposure, and changes in the allowed range of focus and exposure. Different patterns also have different criteria for successful printing. While CD variation of up to +/−15% may be tolerable for some non-critical features, the tolerance for the most critical structures may be only half as much. The failure modes of different patterns may also be very different. Some patterns may be considered unacceptable due to excessive CD variation, others due to excessive changes in their sidewall profiles, and others may suffer from excessive line end pullback or corner rounding. Catastrophic pattern failures are also possible due to the interaction of neighboring structures. A CD variation that may be acceptable if a given feature were being printed as an isolated structure might cause bridging, necking, or other unacceptable pattern variations in a different local environment.
The ultimate goal of the lithography process is to deliver a robust and well maintained “common process window,” that is, a process window in which every feature prints within specifications. An example of the overlapping of multiple process windows for individual structures leading to a common process window is shown in FIG. 3. The more different types of structures one desires to print with acceptable pattern fidelity in a single exposure, the more individual process windows need to overlap successfully and the tighter the overlapping common process window usually becomes. This common process window may also be plotted as a series of overlapping ED trees, and has been referred to in the literature as an “ED forest.”
OPC is one of a number of techniques available to lithography process designers to optimize the process window overlap between all critical features by adjusting the mask level pattern so that, in principle, all patterns are reproduced at the desired wafer dimensions and shapes under a common set of focus and exposure conditions. However, due to the complex non-linear nature of the pattern transfer process, OPC remains a difficult technique to implement, test, and insert into production with the assurance that all features of interest are correctly transferred from mask to wafer in a manufacturing fab. It is particularly difficult to determine which limited set of structures should be measured and tracked on a regular basis to guarantee that all of the structures in the circuit design are printed correctly.
The definition of common process window used to this point has been phrased in terms of CD performance as the sole metric of process capability. In fact, the common process window for a viable process must be such that the entire three-dimensional pattern is replicated faithfully, including the sidewall profile and height of the remaining resist pattern after development. A complete, common process window would insure that the CD, sidewall angle (SWA), and resist loss (RL) during development are all within specifications for all structures in the circuit layer being patterned. In practice, the process window is often defined only in terms of the CD. A typical process window may be defined as the region of the F-E plane over which the critical dimensions are patterned within specified tolerances, such as +1-10% of the nominal target dimension.
In addition to focus and exposure, many other parameters can have an adverse impact on the common process window, including, but not limited to, lens aberrations (Zernike aberrations, scattered light, and other mid- to long-range spatial frequency errors), imperfections in the exposure tool illumination system (uniformity, localized partial coherence, and localized variations in pupil filling), and less than optimal optical proximity corrections. (See Wong, “Resolution Enhancement Techniques in Optical Lithography,” SPIE Press, Bellingham, Wash., Volume TT47, ISBN 0-8194-3995-9 (2001), and Mahajan, “Aberration Theory Made Simple,” SPIE Press, Bellingham, Wash., Volume TT06, ISBN 0-8194-0536-1 (1991)).
A typical integrated circuit device contains between 100 million to several billion structures, and there are typically several hundred devices or chips on a typical silicon substrate with a diameter of 200 or 300 mm. It is clearly impossible to measure the dimensions of every structure on a single device, and even more so to measure every device on every production wafer. In practice, a limited set of structures is defined, either within the device areas or placed in the scribe lines between device areas, for in-process monitoring and control.
One of the most difficult challenges in implementing complex OPC into production, such as leading edge model-based OPC, is the difficulty in determining which limited set of structures should be measured and tracked on a regular basis to guarantee that all of the structures in the circuit design are printed correctly. Since all patterns respond differently to changes in focus, exposure, and other process variables, a test structure that is sensitive to one parameter that must be monitored and controlled may be insensitive to other critical parameters. Thus, even if the process monitors seems to indicate that the process is in control, other patterns which are critical to the proper operation of the device may drift without being detected by the metrology plan of record. Insuring that all of the critical parameters are adequately monitored and controlled is a growing challenge in integrated circuit manufacturing.
In today's wafer fabs, exposure tool related optical conditions such as focus, exposure, illumination and aberration may be monitored using test masks and test wafers using specially designed test patterns, or by an exposure tool's self-metrology while undergoing maintenance checks. The optical analysis in these approaches is not in-situ, i.e., the extracted optical conditions are not present when product wafers are printed. Therefore the use of these data is limited.
It is also possible to use test patterns in the product mask's scribe lines, i.e., the spaces between the device areas, to print test patterns, and analyze the test patterns in the scribe lines to extract the optical conditions when the wafer is printed. This approach will take up the valuable space in the scribe lines, where many other patterns are needed, for example alignment patterns. Furthermore, this approach cannot analyze the optical conditions inside the device design itself.
In practice, a limited set of test structures is defined, either within the device areas or placed in the scribe lines between the device areas, for in-process metrology and process control. The dimensions of these test structures are usually chosen to be at or near the minimum feature size that will be patterned within the device, and are referred to as “the CD” of the layer being patterned regardless of whether the width of the structures being measured is actually the minimum or most critical dimension in the device.
The CD is intended to be measured as near as possible to the base of the three-dimensional resist structure, that is, at the resist-substrate interface, to assure the optimum feature size for subsequent process steps such as etch, film deposition, polishing, and ion implantation. This is often difficult due to the top-down viewing angle of scanning electron microscopes used for CD metrology (CD-SEMs) and the high aspect ratio of the three-dimensional profiles, which typically approach 3:1 (3 units depth in the z-direction for every one unit of width in the x-y plane). Scatterometry (SCD) and tilt-SEMs are intended to help resolve this problem and may be used to determine metrics of resist profile and resist loss in addition to CD, but they suffer from other sources of error and uncertainty as well. While it is possible to obtain a reasonable approximation of the CD at the resist-substrate interface for the specified test structures when the process is very close to optimal, the uncertainty in the true CD increases as the process drifts away from the optimal settings.
CD data from multiple test structures with different geometries may be collected in an effort to more closely monitor the common process window of the entire pattern transfer process. While this comes closer to monitoring the full process than simply measuring a single type of test structure, it falls far short of the ultimate goal of representing the performance of all patterns and structures within the device, including the effects of the local environment on the dimensional stability of each pattern. In addition, a full characterization of the common process window would need to take into account the full three-dimensional shape of the metrology patterns, including sidewall angle, sidewall curvature, or other deviations from an idealized trapezoidal shape, and the height of the pattern indicating resist loss from the top of the three-dimensional structure.
The non-linear manner in which each different structure responds to its own local environment and to the global changes in optical and other process conditions throughout the pattern transfer process from mask to wafer creates a complex manufacturing environment where it is difficult to determine, from a limited number of measurements, whether or not all of the desired features within the device are printed within specification, and whether or not all of the variable process condition parameters are being maintained at or near their optimum operating points. This leads to several related problems:
(1) The limited amount of metrology data and test structures cannot adequately ensure that the CDs across the device are within specifications and that the entire device will operate as intended. Since typical manufacturing cycle times can take several months, it is extremely disruptive to the entire business when a large number of wafers turn out to have unacceptably low yield of devices that work properly, requiring new lots to be started and deliveries to be substantially more expensive and behind schedule.
(2) Even when a variation in CD performance is detected, the proper corrective action to take is often unclear due to the confounding influences of focus, exposure, and other process conditions. Historically the easiest adjustment to make has been the exposure dose (See Levinson, “Lithography Process Control,” SPIE press, Bellingham, Wash., Vol. TT28, ISBN 0-8194-3052-8 (1999)). However, this blind correction, that is, using only a single adjustable parameter to force a desired output on a limited set of data regardless of which of many parameters actually caused the process to deviate in the first place, often means that the root cause of the CD variation remains undetected and incorrectly compensated.
(3) If the process variation of the test structures was caused by a drift or shift in other parameters besides exposure, a simple exposure compensation or other blind adjustment may be adequate to correct the CD of the test structures, but not of all structures within the device, which could result in the final devices having reduced functionality and yield.
(4) Although crude correction such as a blind exposure dose adjustment may bring the metrology target CDs back into specification, if the error was in fact caused by a focus drift or other optical error instead of an exposure drift, the resulting resist profiles will not have the correct sidewalls intended for the process. Thus, when the wafers are etched, the final profile of the resulting etched structure may be incorrect, leading to improper circuit operation and device failure.
(5) Even if the wafers in question are adequately corrected by a simple dose or other blind correction, other wafers that are to be patterned with other device layouts may be patterned incorrectly with the same relative correction. Thus, by changing the only one parameter to compensate for drifts in other parameters, the process control algorithms for the entire production line may become unstable.
(6) Even if the process can be adequately corrected with a global adjustment of the exposure dose or some other blind correction, if the underlying source of the process variation is not correctly identified and corrected, it may continue to drift further until no amount of compensation of a single parameter can recover the desired process outputs. At that point, the orderly flow of wafers through the entire process line may be disrupted as CDs begin to fall outside the specification limits and the root cause analysis of the true source of the variation must be initiated at great cost and disruption to the manufacturing environment.
Many different approaches have been developed to try to improve CD monitoring and control systems. In particular, a number of techniques have been disclosed to try to separate out the influences of focus and exposure to solve some of the problems listed above. While some of these methods are partially successful, they all suffer from drawbacks in terms of metrology calibration and/or requirements for extensive test structures that do not adequately represent the circuit features. In addition, they are limited to focus and exposure only and do not include other optical parameters of interest. Many of these techniques require extensive metrology and test structure calibration and cannot be easily adapted to changes in circuit design and/or process targets.
U.S. Pat. No. 6,414,326 to Nguyen discloses a simple method to deconvolve focus and exposure errors by measuring two different test structures, one with an isolated pitch and the other with a dense pitch. Since these pitches respond differently to focus and exposure, a given combination of CD errors for the respective patterns should correspond to a unique set of focus and exposure errors. Like many similar efforts, this approach still suffers from an ambiguity in the sign of the focus error: a given combination of isolated and dense CD errors could be due to a focus shift of a given magnitude but in either the positive or negative direction. Nguyen teaches a possible solution using astigmatism of the lens to differentiate between the two focus directions for vertically vs. horizontally oriented features, but this requires extensive characterization of lens astigmatism across the field which may also be convolved with other lens parameters.
U.S. Pat. No. 6,673,638 to Bendik et al. discloses a system for creating line end test structures that are modified to print in a deliberately defocused state even when the exposure tool is at best focus. A comparison between differently modified structures can uniquely determine dose and focus errors; the sign ambiguity of the focus can be solved by printing features of opposite polarity (lines and spaces). This approach is restricted to special targets in the scribe line, not actual device geometries, and depends on line end metrology, which is less precise and more susceptible to convolution with other optical aberrations than line width (CD) measurements.
U.S. Pat. No. 6,929,892 to Shishido et al. discloses the use of an SEM with tilt capability or scatterometry to determine the sidewall profile of a highly isolated feature, which is known to be more susceptible to focus-induced variations than dense structures. The ambiguity in the sign of the focus error is said to be resolved by measuring isolated structures of opposite polarity. Like U.S. Pat. No. 6,673,638, this approach is limited to scribe line test structures, not actual device geometries, and the focus sensitive isolated structures are also sensitive to other aberrations.
U.S. Pat. No. 6,803,995 to Ausschnitt discloses a focus control system using special scribe line patterns wherein line end shortening of the segments of a long pattern (“schnitzl”) can be imaged as line width changes in an optical measuring system. The effects of focus and exposure can be deconvolved using targets of opposite polarity, but the sign ambiguity of the best focus position can only be resolved by exposing some fields on the wafer at deliberately defocused conditions, resulting in potential lost chips and complicated exposure and metrology schemes. U.S. Pat. No. 6,643,596 to Firth et al. also discloses a system of deliberately inducing focus perturbations on a lot-by-lot basis to update a focus model. This results in better focus metrology at the expense of negatively impacting the CD control of each lot processed at less than optimal focus.
Various applications of scatterometry have been described as alternative approaches to separating the effects of focus and exposure while also providing CD metrology data. U.S. Patent Application Publication No. 2004/0190008 to Mieher et al. discloses the use of CD, SWA, and RL values derived from SCD spectra to determine a unique combination of focus and exposure conditions. U.S. Pat. No. 6,429,930 to Littau et al. discloses the use of SCD spectra to uniquely determine focus and exposure by comparison to a library of stored spectra and U.S. Patent Application Publication No. 2004/0223137 to Littau et al. discloses extracting an SCD-derived cross section and comparing it to simulated or measured cross sections as a function of F-E conditions. All SCD approaches are limited to arrayed test structures placed in the scribe lines, not device geometries, and are typically limited to one-dimensional line space patterns or at best regular arrays of two-dimensional features such as contact holes. It should also be kept in mind that while SCD does provide highly repeatable measurements, the CD values extracted from SCD curves are all modeled results based on regression, simulation, or lookup tables and do not represent direct measurements of the actual CD or sidewall angle.
Several approaches have been described using signal analysis of the SEM profiles or images to determine the sidewall profile by comparison to stored reference signals. U.S. Patent Application Publication No. 2002/0051567 to Ganz et al. discloses collecting images of assorted structures and comparing them to a library of the same patterns printed at different focus and exposure settings. This technique does not describe how an adequate set of patterns is determined to insure predictability over a range of F-E conditions, or to separate F-E effects from other imaging errors, nor does it result in CD metrology data of sufficient quantitative precision to insure that the process is operating within specifications. U.S. Pat. No. 6,909,930 to Shishido et al. discloses collecting CD-SEM data and analyzing the shape of the SEM line scan profiles or images to determine whether the CD errors are due to focus or exposure. This approach requires extensive calibration, therefore it can only be applied to specific structures which are carefully characterized beforehand and stored in a library. This technique is also sensitive to slight changes in the SEM line scan profile which may be induced by changes in the SEM conditions rather than the exposure tool conditions. U.S. Pat. No. 6,913,861 to Shishido et al. discloses creating special scribe line test structures such as diamond or other highly tapered patterns where the exposure dose is effectively varied along the structure. SEM line scan analysis is performed on these special structures to deconvolve the effects of focus and exposure. U.S. Pat. No. 6,791,082 to Komuro et al. discloses a similar approach using scribe line patterns of opposite polarity to separate the impact of focus and exposure and to resolve the ambiguity in the sign of any focal plane error. Both of these approaches depend on special scribe line targets, not actual device geometries, and rely on extensive look up tables and the stability of the SEM line scan to extract the condition of the exposure tool.
All of the above approaches aim to separate the contributions of focus and exposure on pattern CDs under the tacit assumption that all other optical parameters can be effectively ignored. U.S. Pat. No. 6,795,163 to Finders et al. shows that these other parameters can be as important, if not more so, in determining the patterned CD errors of a given line width as a function of pitch. Finders et al. disclose that the partial coherence, sigma, of the exposure tool can be adjusted to tilt the CD vs. pitch curve to suffer less CD variation across a range of pitches. This illustrates that even in a system that can adequately separate focus and exposure contributions under ideal conditions, the addition of a small illumination error can drastically impact the measured CD performance and so lead to incorrect determination of the computed focus and exposure adjustments.
It is therefore highly desirable to have a system and technique to effectively monitor or observe the lithography process's F-E condition inside the device with actual circuit design patterns, on any selected wafers and at any selected dice on that wafer. This need can be realized by a system and technique that can extract the F-E conditions of the lithographic process directly from printed patterns on product wafers, on any selected wafers and at any selected dice on that wafer.
It is further desired that this system and technique be able to insure the correct patterning of all structures within the device, not just the structure being measured. This need can be realized by a system and technique that can optimize the selection of the optimum set of measured patterns from actual device design patterns that forms a complete characteristic set such that the correct patterning of this set of patterns serves as measurable proof that all patterns within the device are reproduced within specifications.
Beyond the traditional F-E process window, other optical conditions, e.g., NA, illumination conditions, and aberrations, will also drift over time and impact the patterning of the device structures. It is also highly desirable that these other drifts can be extracted directly from the observations of the printed circuit patterns on wafers.
It is further desirable that this system and technique should be capable of quickly and effectively identifying specific patterns within the device that, when measured, will provide precise and specific feedback to the lithography control system indicating not just the CD values, but also the specific corrections that need to be applied to the system to bring the CDs back within specifications and to maintain the exposure tool and the lithography process at their optimum operating conditions. These needs can be realized by the system and technique to locate a complete characteristic set of patterns within the circuit whose collective response to the multivariate optical and process variations provides a unique monitoring and control solution.